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brief_list_of_differences_between_pcb_revisions [2017/06/28 23:40]
z00m
brief_list_of_differences_between_pcb_revisions [2017/06/28 23:47] (current)
z00m
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 \\ \\
  
-===== Detailed differences ​between the versions of the V6Z80P =====+===== Differences ​between the versions of the V6Z80P =====
  
 Summary of the crucial differences with regards to the FPGA connections:​ Summary of the crucial differences with regards to the FPGA connections:​
  
-=== CLOCK INPUT / OUTPUTS: ===+==== CLOCK INPUT / OUTPUTS: ​====
 The earliest version ("​V6Z80P reV1.1"​) of the board has a single oscillator (16 MHz) that drives both the Z80 and FPGA.\\ The earliest version ("​V6Z80P reV1.1"​) of the board has a single oscillator (16 MHz) that drives both the Z80 and FPGA.\\
  
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 The 3rd version of the board ("​V6Z80P+ rev1.1"​) has 2 oscillators (16MHz and 14Mhz), these are connected to GCLK0 and GCLK1. The Z80 clock is sourced from an FPGA output (p75).\\ The 3rd version of the board ("​V6Z80P+ rev1.1"​) has 2 oscillators (16MHz and 14Mhz), these are connected to GCLK0 and GCLK1. The Z80 clock is sourced from an FPGA output (p75).\\
  
-=== Z80 ADDRESS BUS ===+==== Z80 ADDRESS BUS ====
 The earliest version of the board ("​V6Z80P rev1.1"​) loops Z80 signal A15 through the FPGA, allowing 32KB paging of the 512KB system RAM.\\ The earliest version of the board ("​V6Z80P rev1.1"​) loops Z80 signal A15 through the FPGA, allowing 32KB paging of the 512KB system RAM.\\
  
 All other versions loop both A15 and A14 through the FPGA allowing paging down to 16KB.\\ All other versions loop both A15 and A14 through the FPGA allowing paging down to 16KB.\\
  
-=== SPARE PINS ===+==== SPARE PINS ====
 The earliest version of the board ("​V6Z80P rev1.1"​) has 6 "​spare"​ FPGA pins connected to the pin header.\\ The earliest version of the board ("​V6Z80P rev1.1"​) has 6 "​spare"​ FPGA pins connected to the pin header.\\
  
 All other versions have only 5 spare FPGA IO pins connected to the pin header.\\ All other versions have only 5 spare FPGA IO pins connected to the pin header.\\
  
-=== MISC ===+==== MISC ====
 The FPGA pin allocation is completely different between the earliest version of the board ("​V6Z80P rev1.1"​) and all others. Note the pin-outs as listed in text file in the PCB-specific folder (or use the .UCF from the correct version of OSCA).\\ The FPGA pin allocation is completely different between the earliest version of the board ("​V6Z80P rev1.1"​) and all others. Note the pin-outs as listed in text file in the PCB-specific folder (or use the .UCF from the correct version of OSCA).\\
  
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-=== ADAPTING A CONFIGURATION TO WORK ON ALL BOARDS ===+==== ADAPTING A CONFIGURATION TO WORK ON ALL BOARDS ​====
 Obviously if a configuration uses a feature not available on a previous board revision (EG: the 14MHz clock, 16K paging) then it is not possible to directly adapt it work on that board. However, if a configuration uses standard elements common across all boards (as OSCA does) then it is mainly a case of using the correct pin-outs (.UCF file) and checking that: Obviously if a configuration uses a feature not available on a previous board revision (EG: the 14MHz clock, 16K paging) then it is not possible to directly adapt it work on that board. However, if a configuration uses standard elements common across all boards (as OSCA does) then it is mainly a case of using the correct pin-outs (.UCF file) and checking that:
  
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 ===== Full Details ===== ===== Full Details =====
  
-=== V6Z80P v1.1 ===+==== V6Z80P v1.1 ====
  
 This was the first released version. ​ The board is marked "​V6Z80P rev1.1"​. It has an 8-pin mini DIN socket for video and a 4-pin comms socket. There are two LEDs (excluding the SD card LED) for system status.\\ This was the first released version. ​ The board is marked "​V6Z80P rev1.1"​. It has an 8-pin mini DIN socket for video and a 4-pin comms socket. There are two LEDs (excluding the SD card LED) for system status.\\
  
-=== V6Z80P+ V1.0 ===+==== V6Z80P+ V1.0 ====
  
 This board was mainly an experiment with a programmable clock chip. The chip turned out to be unsuitable but the boards were able to be used in a fallback configuration (a different config file to the original V6Z80P is required, however). These boards are marked "​V6Z80P+ Rev1.0"​.\\ This board was mainly an experiment with a programmable clock chip. The chip turned out to be unsuitable but the boards were able to be used in a fallback configuration (a different config file to the original V6Z80P is required, however). These boards are marked "​V6Z80P+ Rev1.0"​.\\
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 \\ \\
  
 +==== V6Z80P+ v1.1 ====
  
-V6Z80P+ ​v1.1 +Made in Jan 2011. This board better allows alternative clock inputs and CPU clock control. The board is marked "V6Z80P+ ​Rev1.1"\\
-------------+
  
-Made in Jan 2011. This board better allows alternative clock inputs +There are two oscillator systems connected to GCLK0 (16MHz for OSCA) and GCLK1 (14MHz for Spectrum Emulation) these are both based on a 74HC04 gate plus timing crystal. There is also a footprint for a 7x5mm SMT 3.3v oscillator module on the underside of the PCB for the GCLK3 input (which also still goes to a header pin, as does GCLK2).\\
-and CPU clock control. The board is marked "​V6Z80P+ Rev1.1"​ +
- +
-There are two oscillator systems connected to GCLK0 (16MHz for OSCA) +
-and GCLK1 (14MHz for Spectrum Emulation) these are both based on a 74HC04 +
-gate plus timing crystal. There is also a footprint for a 7x5mm SMT +
-3.3v oscillator module on the underside of the PCB for the GCLK3 input +
-(which also still goes to a header pin, as does GCLK2).+
  
 A phsysical switch* controls the CPU clock selection in the following way: A phsysical switch* controls the CPU clock selection in the following way:
  
- In the up position, input A to the 74HCT08 AND gate (which outputs +   ​* ​In the up position, input A to the 74HCT08 AND gate (which outputs the level-shifted CPU clock signal) comes direct from the main 16MHz oscillator. In this case, AND input B (from pin 75 of the FPGA) should normally be pulled up.  
- the level-shifted CPU clock signal) comes direct from the main 16MHz +   * In the down position, input A is pulled high by a resistor. In this state, pin 75 from the FPGA needs to deliver the clock signal (the FPGA can loop through - and (if desired) gate - whichever GCLK signal is required for the project).
- oscillator. In this case, AND input B (from pin 75 of the FPGA) should +
- normally be pulled up. +
  
- ​In ​the down position, ​input A is pulled high by a resistorIn this state,  +(* The switch was included for 100% OSCA compatibility with the V6Z80P plus V1.0 config files (up position). Howeverit is more convenient to just leave the switch in the down position and use the V6Z80Plus V1.1 config files. (These are almost ​the same as the V6Z8op+ 1.0 configs: the only difference is that on the v6z80p+v1.1,​ the 16MHz system ​clock is looped through ​the FPGA and output to pin 75, whereas on the v6z80p+ v1.0 pin 75 is just pulled high).\\
- pin 75 from the FPGA needs to deliver ​the clock signal (the FPGA can loop +
- ​through - and (if desired) gate - whichever GCLK signal is required for the +
- ​project).+
  
- ​(* ​The switch was included for 100% OSCA compatibility with the V6Z80P +The serial comms socket has reverted back to being a 4-pin mini DIN (same pin out as original V6Z80p).\\
- plus V1.0 config files (up position). However, it is more convenient ​to +
- just leave the switch in the down position and use the V6Z80Plus V1.1 config +
- ​files. ​(These are almost the same as the V6Z8op+ 1.0 configs: the only +
- ​difference is that on the v6z80p+v1.1,​ the 16MHz system clock is looped +
- ​through the FPGA and output to pin 75, whereas on the v6z80p+ v1.0 pin 75 is +
- just pulled high)+
  
-The serial comms socket has reverted back to being a 4-pin mini DIN (same pin +The through-hole EEPROM footprint and programmable clock chip footprint have been removed.\\
-out as original V6Z80p)+
  
-The through-hole EEPROM ​footprint ​and programmable clock chip footprint +The 3.3v regulator for the SD card now uses a SOT223 ​footprint ​instead of SOIC-8.\\
-have been removed.+
  
-The 3.3v regulator for the SD card now uses a SOT223 footprint instead +The PCB mounting holes are in different locations.\\ 
-of SOIC-8 +\\
- +
-The PCB mounting holes are in different locations. +
- +
- +
-V6Z80P+ v1.1b +
-------------- +
- +
-Made in March 2011 this board has the same main features as the V6Z80P+ v1.1 +
-(and uses the same config files). The following changes were made: +
- +
-The board is marked "​V6Z80P+ Rev1.1b"​+
  
-The "OSC SEL" switch has been removed - the CPU clock is now always supplied +==== V6Z80P+ ​v1.1b ====
-via the FPGA (electrically,​ it is the same as the V6Z80P+1.1 with the OSC SEL +
-switch down)+
  
-The SD card connector is an enclosed, push-push type and located ​in a slightly +Made in March 2011 this board has the same main features as the V6Z80P+ v1.1 (and uses the same config files). The following changes were made:
-different position+
  
-There are wider pads for the 8-pin EEPROM+   * The board is marked "​V6Z80P+ Rev1.1b"​ 
 +   * The "OSC SEL" switch has been removed - the CPU clock is now always supplied via the FPGA (electrically,​ it is the same as the V6Z80P+1.1 with the OSC SEL switch down) 
 +   * The SD card connector is an enclosed, push-push type and located in a slightly different position.  
 +   ​* ​There are wider pads for the 8-pin EEPROM
  
brief_list_of_differences_between_pcb_revisions.txt · Last modified: 2017/06/28 23:47 by z00m