User Tools

Site Tools


PCB revisions


V6Z80P v1.0

Boards produced: None.

V6Z80P v1.1

Boards produced: about 40.
Revision reasons: Changed IC footprints.

V6Z80P+ v1.0

Boards produced: 10.
Revision reasons:

  • Use VGA socket for video, instead of mini-din socket (adapter cable now only required for SCART)
  • Provide alternative FPGA clock inputs via header pins.
  • Provide gated CPU A14 signal (allows 16KB paging)

Other changes:

  • 3-pin mini-DIN socket for serial port.
  • Support for Sega megadrive joysticks.

V6Z80P+ v1.1

Boards produced: 10
Revision reasons:

  • Allow FPGA to drive CPU clock.
  • 74HC04+crystal oscillator footprint allowing 14MHz alternative oscillator, giving 7MHz pixel clock and 3.5MHz CPU clock for Spectrum emulator).

Other Changes:

  • EEPROM footprint is SMT only.
  • 4-pin mini DIN socket for serial port.

V6Z80P+ v1.1b

Boards produced: 10
Revision reasons:

  • SD card connector is now push-push type (due to difficulty in sourcing type originally used). Card slot is in a slightly different position (surrounding components moved to make space too.)
  • Removed “OSC SEL” switch (unnecessary)
  • Wider pads to accomdate SOIC-W 8-pin style EEPROM (PIC code supports SST25VF32).

Differences between the versions of the V6Z80P

Summary of the crucial differences with regards to the FPGA connections:


The earliest version (“V6Z80P reV1.1”) of the board has a single oscillator (16 MHz) that drives both the Z80 and FPGA.

The 2nd version of the board (“V6Z80P+ rev1.0”) has an output (p75) from the FPGA that can act as a clock enable to Z80 (pull this pin up in config for normal use).

The 3rd version of the board (“V6Z80P+ rev1.1”) has 2 oscillators (16MHz and 14Mhz), these are connected to GCLK0 and GCLK1. The Z80 clock is sourced from an FPGA output (p75).


The earliest version of the board (“V6Z80P rev1.1”) loops Z80 signal A15 through the FPGA, allowing 32KB paging of the 512KB system RAM.

All other versions loop both A15 and A14 through the FPGA allowing paging down to 16KB.


The earliest version of the board (“V6Z80P rev1.1”) has 6 “spare” FPGA pins connected to the pin header.

All other versions have only 5 spare FPGA IO pins connected to the pin header.


The FPGA pin allocation is completely different between the earliest version of the board (“V6Z80P rev1.1”) and all others. Note the pin-outs as listed in text file in the PCB-specific folder (or use the .UCF from the correct version of OSCA).

The FPGA pin allocation between the two later “V6Z80P+” boards is the same except for the label:

“Z80_CLOCK_ENABLE” (p75) becomes “Z80_CLOCK” on the latest board “V6Z80P+ rev1.1”


Obviously if a configuration uses a feature not available on a previous board revision (EG: the 14MHz clock, 16K paging) then it is not possible to directly adapt it work on that board. However, if a configuration uses standard elements common across all boards (as OSCA does) then it is mainly a case of using the correct pin-outs (.UCF file) and checking that:

  1. The clock input/output should be handled correctly for each board. EG: Simply loop the clock signal through the FPGA Input→output on the latest board. (Pull the clock_enable high on the V6Z80P+reV1.0.)
  2. Z80 A14 should be looped straight through the FPGA Input→Output on the later boards that support this feature.
  3. All FPGA configs should hold the Z80 reset signal low for a while on start up to ensure reliable code execution.

Full Details

V6Z80P v1.1

This was the first released version. The board is marked “V6Z80P rev1.1”. It has an 8-pin mini DIN socket for video and a 4-pin comms socket. There are two LEDs (excluding the SD card LED) for system status.

V6Z80P+ V1.0

This board was mainly an experiment with a programmable clock chip. The chip turned out to be unsuitable but the boards were able to be used in a fallback configuration (a different config file to the original V6Z80P is required, however). These boards are marked “V6Z80P+ Rev1.0”.

There is a standard 15-pin VGA connector for video output and a 3 pin mini-din serial comms socket.

There is only one system status LED (excluding the SD card LED).

The joystick ports supply 3.3v to pin 5 via 22ohm resistors (this should make them Megadrive pad compatible).

There are now only 2 spare IO port header pins.

There are alternative (SMT) footprints for the onboard EEPROM.

The PCB mounting holes are in different locations.

Clock / FPGA pin changes:

CPU signal A14 is now routed through the FPGA (as well as A15) this means 16KB paging can be performed on system memory if desired.

GCLK2 and GLCK3 are now routed to pin headers on the left hand side. (The other unused GLCK is connected to a footprint for a programmable clock chip. However, this turned out to be unsuitable so was omitted from the circuit).

There is now a line out from the FPGA (p75) to the input B of the 74HCT08 AND gate that controls the Z80 clock (the main oscillator drives input A). Normally this should be pulled high by the FPGA.

The config PIC chip now uses a crystal for its oscillator (because it was anticipated that the main system clock would be variable). The pin connections were also changed, so the .HEX file for this PIC is different to the original V6Z80P.

V6Z80P+ v1.1

Made in Jan 2011. This board better allows alternative clock inputs and CPU clock control. The board is marked “V6Z80P+ Rev1.1”

There are two oscillator systems connected to GCLK0 (16MHz for OSCA) and GCLK1 (14MHz for Spectrum Emulation) these are both based on a 74HC04 gate plus timing crystal. There is also a footprint for a 7x5mm SMT 3.3v oscillator module on the underside of the PCB for the GCLK3 input (which also still goes to a header pin, as does GCLK2).

A phsysical switch* controls the CPU clock selection in the following way:

  • In the up position, input A to the 74HCT08 AND gate (which outputs the level-shifted CPU clock signal) comes direct from the main 16MHz oscillator. In this case, AND input B (from pin 75 of the FPGA) should normally be pulled up.
  • In the down position, input A is pulled high by a resistor. In this state, pin 75 from the FPGA needs to deliver the clock signal (the FPGA can loop through - and (if desired) gate - whichever GCLK signal is required for the project).

(* The switch was included for 100% OSCA compatibility with the V6Z80P plus V1.0 config files (up position). However, it is more convenient to just leave the switch in the down position and use the V6Z80Plus V1.1 config files. (These are almost the same as the V6Z8op+ 1.0 configs: the only difference is that on the v6z80p+v1.1, the 16MHz system clock is looped through the FPGA and output to pin 75, whereas on the v6z80p+ v1.0 pin 75 is just pulled high).

The serial comms socket has reverted back to being a 4-pin mini DIN (same pin out as original V6Z80p).

The through-hole EEPROM footprint and programmable clock chip footprint have been removed.

The 3.3v regulator for the SD card now uses a SOT223 footprint instead of SOIC-8.

The PCB mounting holes are in different locations.

V6Z80P+ v1.1b

Made in March 2011 this board has the same main features as the V6Z80P+ v1.1 (and uses the same config files). The following changes were made:

  • The board is marked “V6Z80P+ Rev1.1b”
  • The “OSC SEL” switch has been removed - the CPU clock is now always supplied via the FPGA (electrically, it is the same as the V6Z80P+1.1 with the OSC SEL switch down)
  • The SD card connector is an enclosed, push-push type and located in a slightly different position.
  • There are wider pads for the 8-pin EEPROM
brief_list_of_differences_between_pcb_revisions.txt · Last modified: 2017/06/28 23:47 by z00m