Version names ending in 'N' are for NTSC TV
Version names ending in 'P' are for PAL TV
Both support VGA output.
Updates to OSCA
Latest version
v676
THIS VERSION OF OSCA REQUIRES BOOTCODE v618, UPDATE BOOTCODE FIRST IF NECESSARY
mult_write, mult_read and mult_index are now also accessible through Z80 IO ports
mult_read/mult_write = port $28 (sys_mult_read, sys_mult_write)
mult_index = port $2a (sys_mult_index)
Previous versions
v675
THIS VERSION OF OSCA REQUIRES BOOTCODE v618 TO BE INSTALLED FIRST
28800 and 14400 BAUD support and IRQ feature added to serial port
PS/2 Interfaces updated: Now hold clock lines low when “byte_received_flag” is set
Video Interrupt can be enabled via normal “sys_irq_enable” port
Audio interrupt moved to bit 4 of IRQ enable
v674
The upper 4 bits of the OSCA version ID now contain a PCB version code (1=V6Z80P, 2=V6+V1.0, 3=V6+v1.1)
PS/2 Interface modules changed to synchronous logic.
PS/2 interface write signal input changed to delayed CPU write (was using raw CPU write)
v673
v672
v671
v670
v669
v668
v667
v665
v664
Video RAM window can be moved from default location $2000 to any 8KB boundary of Z80 address space (added the setting sys_vram_location @ port $21)
Includes ROM 6.15 (resets sys_vram_location on reset)
v663
v661
ROM version updated to v6.14 (requires bootcode 6.12)
Port $B (“sys_alt_write_page”) is now readable
When VGA mode is not selected H_Sync is now high (V6Z80P+ compatibility)
v660
Change: The PAL and NTSC versions of OSCA now only contain the relevant sync generator. So to switch to the other TV system, it is necessary to put the alternative config in another slot and reconfigure the FPGA.
New: Port bit option to force VGA output to 50Hz (312 lines)
New: 8×8 Tilemode added
Change: Extended mode tilemaps are now positioned at $70000
From this version backwards, the only difference between the PAL and NTSC versions of the OSCA config/project was that the NTSC mode flip/flop (bit 2 in Z80 Port 9) is set by default in the NTSC version - it can be switched in software.
v659
Made port $20 readable.
Reset button now clears “sys_alt_write_page”, meaning the ROM is paged in upon reset so the system can always start.
Reset logic simplified (optimization)
ROM updated (v612) - Port $20 is cleared on startup.
v658
Added ability to select the 32KB bank of system RAM that resides at CPU address $0-$7fff (port $20).
Added a control bit to allow the first 32KB of system RAM to appear at CPU address $8000-$7fff.
Schematics for Port decode / registers tidied up in Xilinx project.
v657
v656
ROM/Palette can now be paged out (0-$1ff = system RAM when bit 6 of port sys_alt_write_page is set)
When Video registers are paged out (with bit 7 of port sys_alt_write_page) $200-$7ff becomes system RAM (previously $700-$7ff was exluded)
Because of the above, the video status register “vreg_read” at $700 is now also available in port 7 (sys_vreg_read)
v654
v652
ROM updated to load new bootcode (6.11)
Port “sys_alt_write_page” bit 7 now pages out the hardware registers in the range $200-$6ff when set. The locations always READ as the system memory, and can be written to (without affecting the video registers) when the new option bit is set.
v651
Fixed the Video IRQ flag (vreg_read bit 3) which at some point I'd accidentally connected to the video IRQ enable line, instead of the video IRQ status flag signal.
Tidied up video register schematics. Removed some async logic and negative clock logic. Fixed an unconnected input that had gone unnoticed.
Compiled with “keep hierachy: soft” - seems to work fine.
v650
Writes to Live Palette Select bit now take effect at the start of the next scanline.
Modulo register special case: When $ff is written, the data-fetch offset counter is cleared at the start of each scan line (so the same background line is re-used repeatedly)
When sprite height is set to zero, sprite is 240 pixels tall (doesn't apply if matte mode is enabled)
New sprite priority mode bit: Allows sprites that are forced to the foreground by setting their height MSB to 1 (via priority mode) to maintain colours in the palette range 1-127, instead of changing to 129-255.
v645
v642
v641
v638
v635
v634
v630
v624
Despite the sole change being the addition of an inverter gate on the display mode jumper, v623 appeared to have a bug which froze the system, particularly when scrolling the screen in FLOS. This version is an attempt to fix that. It also contains a small ROM update (if bootcode CRC is bad, screen flashes magenta if bootcode databurst times out, screen flashes yellow)
v623
v622
618
ROM 6.01: clear blit_src_msb and blit_dst_msb on boot to help backwards compatibility with v5z80p programs (if a v6z80p program changed these from default zeroes, and then a v5z80p program ran afterwards, the blitter would use incorrect locations, ie: above 128KB in VRAM)