The V6Z80P is based around a Xilinx Spartan 2 XS2S150 FPGA, Zilog 20MHz Z80 and 3 SRAM memory ICs. Also onboard are two PIC chips (one handles FPGA configuration, whilst the other is used as a parallel-to-serial converter for the joystick inputs), an SPI EEPROM (which holds FPGA config patterns and other data), an ST232 voltage convertor for serial comms and a 74HCT08 quad AND gate (for CPU clock and reset, see descriptions below).

1. 512KB SRAM 10ns, 3.3v - direct connection to FPGA /CS permanently active (pulled low).
2. 128KB SRAM 10ns, 3.3v direct connection to FPGA, /CS permanently active (pulled low).
3. 512KB SRAM 25ns, 5v. Some connections direct to CPU and FPGA, some are routed through the FPGA (see description below). This chip is referred to as “System RAM”.

All Z80 control pins (except CLOCK, /RFSH and /HALT) are connected to FPGA pins. /RD, /WR and D0:D7 and A0:A14 are also connected direct to System RAM. To allow 32KB memory paging, A15 is routed through the FPGA, (On the V6Z80P+, A14 is also routed through the FPGA allowing 16KB paging) System RAM lines A18:A16 are driven direct from the FPGA.

The Z80 / RESET signal is also connected to the output of an 74HCT08 AND gate: AND input A is connected to the FPGA's DONE signal, and input B is connected to an FPGA output pin. This means the Z80 is held in reset state until the FPGA has started, and can also be reset by the FPGA. (FPGA configurations should pull this reset line low for a short period upon start up to guarantee CPU reset time with the clock running)

The Z80's clock signal is driven by the output of a 74HCT08 gate, the inputs of this gate are connected differently depending on the version of the board:

• AND gate input A is connected to the 16MHz oscillator, input B is pulled high.

• AND gate input A is connected to the 16MHz oscillator, input B is connected to an FPGA pin (p75). Normally, the FPGA pin should be pulled high.

• AND gate input A can either be connected to the 16MHz oscillator or pulled high - an onboard switch called “OSC SEL” selects the operating mode:
  • When the switch is down, input A is pulled high, and the CPU clock signal should be supplied to Input B from the FPGA (pin 75).
  • When the switch is up, input A is connected to the 16MHz clock, so input B (p75) should normally be pulled high.

(The OSC SEL only needs to be up position if using FPGA configs designed for the V6Z80P+ V1.0)

• There is no OSC SEL switch, the board is wired as if the switch were fixed in the down position, IE: the CPU clock always comes from the FPGA.

The 2×5 pin header has 6 pins connected directly to general purpose FPGA IOs (5 on the V6Z80P+) they have no fixed purpose (in OSCA they are used for NMI, RESET and VGA select, with the others configured as Z80 I/O ports). The layout of the pins depends on the model of V6Z80P:

                G 0  --> FPGA pin 148
                G 1  --> FPGA pin 149
                G 2  --> FPGA pin 150
                G 3  --> FPGA pin 151
FPGA pin 160--> 4 5  --> FPGA pin 152

        N  G  G  G  G
        0  1  2  3  4 ----->FPGA pin 148
        |  |  |  '--------->FPGA pin 149
        |  |  '------------>FPGA pin 150
        |  '--------------->FPGA pin 151
        '------------------>FPGA pin 152

The V6Z80P+ boards also have a 3×1 pin header connected to the FPGA's unused GCLK inputs:

        G  5  6 --> FPGA pin 185
           '------> FPGA pin 182

G = Ground, N = No connection

12 FPGA outputs drive three 4-resistor DACs for Red, Green and Blue analog outputs (which allows a palette of 4096 colours). The RGB levels (once connected to standard 75Ohm loads) are < 0.7v suitable for TV for VGA monitors. 2 additional FPGA outputs drive Horizontal sync and Vertical sync outputs. The connections vary, depending on the model of V6Z80P.

• An 8 pin mini-DIN socket is used for video out, so custom cables are required for both VGA and TV displays. The outputs are:
  • “Select” (5volts, via 100Ohms), Ground, Red, Green, Blue, V-sync (TTL), H-Sync (TTL),
  • “Composite Sync” (V-Sync via 750 Ohms).

• A standard 15 pin VGA connector is used so a custom cable is only required for TV displays. The outputs are:
  • Ground, Red, Green, Blue, TTL V-Sync (via 100 Ohms), TTL H-sync (via 100 Ohms).
  • The custom SCART TV cable connects TTL V-Sync to Composite sync via 660Ohms, this then presents the correct analogue voltage level. TTL H-sync is connected to the SCART “Select” line to active RGB mode - note that that the FPGA must be aware that TV mode is being used, so it can pull-up the H-Sync line continually.

Two outputs from the FPGA (Sigma/Delta pulse trains) drive a simple resistor/capacitor filter. The output of which has its amplitude halved by a potential divider (2 x 10K), passed via 1uf capacitor to the left and right of the 3.5mm audio socket.

A 4-pin mini DIN (3-pin on the V6Z80P+ V1.0) is used for the V6Z80P com port (to avoid confusion with the joystick ports) RX, TX and Ground are connected. The lines are routed via a ST232 level converter chip to and from the FPGA.

Keyboard and mouse. CLOCK and DATA are directly connected to FPGA (and pulled up to 5v via 10K resistors). These lines can be pulled down (for output) by transistors connected to the FPGA.

There are two Atari 2600 / Amiga style connectors: 6 inputs each. All lines are pulled up by resistors and pulled down by the switches in the joystick. The 12 lines are connected to a PIC 16F627A (or occasionally 16F628A) microcontroller acting as a parallel-to-serial converter. Two FPGA pins for Clock and Data are used to read the joystick data from the PIC. On the V6Z80P+, pin 5 of the joystick ports is pulled to 3.3v via 22 Ohm resistors to allow Megadrive/Genesis pads to work also (with these pads, Fire #1 is the B button, Fire #2 is the C button).

Uses 5 FPGA pins to connect to Power, /Card Select, Data_in, Data_out and Clock. /Card select is also connected to an LED via resistor for access indication. The FPGA /Power line switches a PNP transistor to apply power to the card.

The PIC-based configuration system uses several FPGA pins to upload config data and communicate with the PIC after config (includes reprogramming the EEPROM etc)

Used for “live” configuration of the FPGA, standard Xilinx pin out sequence.

(J1 and J2, where marked) These select between JTAG config mode and normal EEPROM configuration (slave serial mode). For JTAG configuration both jumpers should be installed.

Full pin outs and more details of the PCB can be found in the “Specifics” folders.

The earliest version (“V6Z80P reV1.1”) of the board has a single oscillator (16 MHz) that drives both the Z80 and FPGA.

The 2nd version of the board (“V6Z80P+ rev1.0”) has an output (p75) from the FPGA that can act as a clock enable to Z80 (pull this pin up in config for normal use).

The 3rd version of the board (“V6Z80P+ rev1.1”) has 2 oscillators (16MHz and 14Mhz), these are connected to GCLK0 and GCLK1. The Z80 clock is sourced from an FPGA output (p75).

The earliest version of the board (“V6Z80P rev1.1”) loops Z80 signal A15 through the FPGA, allowing 32KB paging of the 512KB system RAM.

All other versions loop both A15 and A14 through the FPGA allowing paging down to 16KB.

The earliest version of the board (“V6Z80P rev1.1”) has 6 “spare” FPGA pins connected to the pin header.

All other versions have only 5 spare FPGA IO pins connected to the pinheader.

The FPGA pin allocation is completely different between the earliest version of the board (“V6Z80P rev1.1”) and all others. Note the pin-outs as listed in text file in the PCB-specific folder (or use the .UCF from the correct version of OSCA).

The FPGA pin allocation between the two later “V6Z80P+” boards is the same except for the label:

“Z80_CLOCK_ENABLE” (p75) becomes “Z80_CLOCK” on the latest board “V6Z80P+ rev1.1”

Obviously if a configuration uses a feature not available on a previous board revision (EG: the 14MHz clock, 16K paging) then it is not possible to directly adapt it work on that board. However, if a configuration uses standard elements common across all boards (as OSCA does) then use the following checklist:

• a) Use the correct pin-outs for each particular board revision (see the “Documentation/PCB Version Specifics” folders or borrow and adapt a .UCF file from the OSCA project folders).
• b) The clock input/output should be handled correctly for each board. EG: Simply loop the clock signal through the FPGA Input→Output on the latest board. (Pull the clock_enable high on the V6Z80P+reV1.0.)
• c) Z80 line A14 should be looped straight through the FPGA Input→Output on the later boards that support this feature.
• d) All FPGA configs should hold the Z80 reset signal low for a while on start-up to ensure reliable code execution.

1. Power is switched on.
2. Z80 CPU is held reset (by the FPGA's “done” line being low)
3. Config PIC checks JTAG-mode jumper J2 (Note: J1 sets the FPGA itself to JTAG mode)
   • If jumper J2 is installed, the status LED flashes rapidly until the FPGA has been manually configured by downloading a .bit file from Xilinx Impact software on PC.
   • If jumper J2 is not installed, the PIC sends the config data stored in the current active slot of the EEPROM to the FPGA.
4. If the FPGA starts up correctly with the architecture file supplied (ie: the FPGA's “Done” line goes high) the status LED stays on. If the config fails, the status LED will pulse and the PIC goes back to step 3.
5. The Z80 is released from reset and starts executing code from address $0

The V6Z80P has an onboard 25-series SPI EEPROM chip (the capacity varies but it is normally 1MB or more). Mainly, this chip is used to hold the configuration data for the various FPGA architectures (IE: OSCA, Spectrum emulator etc).

The FPGA cannot read an EEPROM such as this directly, therefore a PIC microcontroller (16F627A or 16F628A) is used as a controller. Under normal operating conditions (IE: non-JTAG mode) Upon power on, the PIC tells the EEPROM to send approx 128KB of config data from the EEPROM to the FPGA.

Once the FPGA is configured, the Z80 CPU is released from RESET state and the system starts.

As the EEPROM is large enough to hold several different configuration patterns a custom communications protocol is employed which allows the CPU to talk to the PIC, allowing it to select a differerent config pattern etc. Additionally, the PIC-EEPROM system allows the CPU to read arbitrary data from the EEPROM for uses other than configuration (EG: under OSCA, boot code is required - this is stored in the EEPROM. The default bootcode also allows an OS to be loaded from the EEPROM, although this is normally loaded from SD card).

Aside from the signals required for basic configuration, the following connections are used:

FPGA pin → PIC pin: Data (OSCA's Z80 port sys_pic_comms - bit 0 output)

FPGA pin → PIC pin: Clock (OSCA's Z80 port sys_pic_comms - bit 1 output)

PIC pin → FPGA pin: Clock/Busy (OSCA's Z80 port sys_hw_flags - bit 3 input (also serial-parallel converter clock)

EEPROM output pin → FPGA pin and PIC pin: EEPROM Data (converted to bytes, and read from OSCA's Z80 port: sys_eeprom_byte)

Note that the physical pin connections are different on the various revisions of the V6Z80P, refer to the schematics in the appropriate folder for details. (The OSCA port bit assignments remain constant however.)

Command and argument bytes are sent serially to the PIC MSb first, with bits latched by the PIC on the rising edge of the clock line. Use the OSCA port “sys_pic_comms” to bit-bang the data to the PIC). To prevent bits being missed or the system timing out, the bit rate should be between 2KHz and 100 KHz. If a clock/busy signal is received from the PIC (see OSCA port “sys_hw_flags”) this indicates the data is not acceptible (args out of range etc). Also, use a short delay (around 100 microseconds) between subsequent commands (EG: after a databurst) to allow the PIC to return to its “waiting for command” state.

Configuration-related

$88 + $a1

Immediately reconfigure the FPGA from the current config address base

$88 + $b8 + $low + $middle + $high address bytes

Set the config address base

$88 + $37 + $d8 + $06

make the current FPGA config base address permanent (IE: store it in the PIC's flashram. Note: “Programming mode” must be enabled first)

Databurst-related

$88 + $c9

send data to FPGA using current databurst base address and length (Under OSCA, the bit stream is converted into bytes and appears in the port: sys_eeprom_byte)

$88 + $d4 + $low + $middle + $high address bytes

Set databurst address base

$88 + $e2 + $low + $middle + $high count bytes

Set databurst length

Programming-related

$88 + $25 + $fa + $99

Allow EEPROM/PIC programming

$88 + $1f

Disable EEPROM/PIC programming

$88 + $f5 + $low + $middle + $high address bytes

Erase 64KB block of SPI EEPROM ($middle and $low = $00) (Programming mode must be enabled first)

$88 + $98 + $low + $middle + $high address bytes + 64 data bytes

Program 64 bytes into the EEPROM (The 64KB EEPROM block in which the bytes are to be located must be erased prior to programming new data.)

Status-related

$88 + $53 (added in PIC firmware v6.17 - Nov '09)

Request EEPROM sends its size/ID byte (response to SPI command $AB) - Note: if the EEPROM is a SST25VFxxx type, this will return a manufacturer's code ($BF) instead. If this byte is received, use command $88 + $6c (see details below).

Valid bytes returned by this command:

$88 + $76 (added in PIC firmware v6.17 - Nov '09)

Request PIC sends the MSB of the config base address (IE: slot selection * 2) As this data is sent from the PIC and not the EEPROM, it is not received as a byte in the usual port. (See “Reading data from the PIC” below)

$88 + $4e (added in v6.18 - Nov' 09)

Request PIC sends its firmware revision (last two BCD digits of the firmware version. EG: if fw version is 6.18, the byte is $18) The byte is sent in the same way as the active slot.

$88 + $6c (added in V6.35)

Optional EEPROM ID read if Command $88+$53 returns manufacturer's ID ($BF) instead of the capacity. NOTE: data sent by this command is sent by the PIC, not EEPROM)

The location and length of the data required should be sent using the commands as shown above. Next a “send databurst” command sequence is sent to the PIC. Afterwards, the outgoing clock line should be raised (set port sys_pic_comms bit 1) - this prompts the PIC to send eight bits of data. When the bits have been received (in OSCA, the “byte ready” flag in port sys_hw_flags becomes set), the clock line should then be cleared and the byte received read from the port “sys_eeprom_byte”. Whenever this port is read, the serial count and byte received flags are reset. The clock should stay low for at least 4 microseconds (to ensure that the PIC does not miss it). This cycle should be repeated for the all bytes required.

To read a single byte (IE: response from get_EEPROM_ID command $88+$53, just go through the above procedure one time.

To read data from the PIC (as opposed to the EEPROM), a slower, manual method must be used: First send the command that is to return data from the PIC (EG: $88+$76 = get PIC firmware version). Raise the clock (set “sys_pic_comms” port bit 1), wait about 100 microseconds and then reset the clock bit. Read the PIC input line (bit 3 of “sys_hw_flags”) and put this bit into bit 0 of a left shift register (IE: MSb is sent first), wait about 100 microseconds, and then repeat the process for the next 7 bits.

Due to limitations imposed by the EEPROM, the entire 64KB page must be erased before inserting arbitary data into it. Therefore if only a few bytes are required to be changed, the entire page must first be read, the data changed in a buffer, the EEPROM page erased and the new 64KB of data uploaded from the buffer.

Also, although the EEPROM can accept single bytes for programming, the V6Z80P system stipulates that 64 byte packets must be sent. When sending DATA to the PIC, the CPU should check for a clock high from the PIC (OSCA's sys_hw_flags port bit 3). This means the CPU should pause the transmission as the PIC/EEPROM is busy (burning to flashram etc).

The EEPROM memory is arranged as 64KB blocks. In the OSCA/FLOS documentation a “Slot” is two consecutive blocks.

        .---------------. <-$00000
      / !    BLOCK 0    !
SLOT 0  !---------------! <-$10000
      \ !    BLOCK 1    !
        !---------------! <-$20000
      / !    BLOCK 2    !
SLOT 1  !---------------! <-$30000
      \ !    BLOCK 3    !
        !---------------! <-$40000
      / !    BLOCK 4    !
SLOT 2  !---------------! <-$50000
      \ !    BLOCK 5    !
        !---------------! <-$60000
      / !    BLOCK 6    !
SLOT 3  !---------------! <-$70000
      \ !    BLOCK 7    !
        !---------------!
        ! etc etc etc   !

Slot 0 is reserved for OS / bootcode / user data:

Block 0:

• $0000-$07FF: Unused
• $0800-$EFFF: FLOS / other OS can be installed here
• $F000-$FFFF: Primary bootcode

Block 1:

• $0000-$EFFF: Not used
• $F000-$FFFF: Backup bootcode

The other slots can each take a spartan II XS2S150 FPGA config .bin file (or other arbitrary user data).

A PIC microcontroller is used to read 2 x 6 pin digital inputs from Atari/Amiga standard 9 pin D-Sub connectors and send data serially to the FPGA using two pins: Clock and Data. The FPGA provides the clock, Data is always PIC → FPGA.

Data bits are output following detection of a rising edge on READ_CLOCK_IN The FPGA therefore latches each bit on the following clock high edge.

 ACTION......    Latch 0    Latch 1     

          ____      V_____      V_____
 CLOCK __!    !_____!     !_____!     !____ 

 DATA------<===BIT 0==><==BIT 1===><==BIT2==>

When the clock stays low for more than ~300 microseconds, the data packet send is aborted, new joystick values are read from the ports and the data transmission begins on the next clock high.

Transmission is a 16 bit word in the following order:

(Joy A) U,D,L,R,F1,F2, 0,0, (Joy B) U,D,L,R,F1,F2, 0,0

See the board specific schematics for physical pin connections as these vary across the V6Z80P revisions.