OSCA contains a boot ROM as part of its FPGA config file (it is implemented as a 512 byte blockRAM). This is normally mapped into $0000-$01FF of Z80 address space (but can be paged out with bit 6 of the port sys_alt_write_page). The ROM code's job is to load the main boot code from the onboard EEPROM:

The ROM looks for the bootcode at two locations:

EEPROM Block 0: $F000 [Primary bootcode location]
EEPROM Block 1: $F000 [Backup bootcode location]

To test for bootcode, a “databurst” command is sent to the PIC microcontroller which responds by sending 3520 bytes from the EEPROM. The ROM reads this data into system RAM $0200 onwards, checks the CRC checksum (held in the last two bytes) and executes it (with a JP $200) if the checksum is good.

(If the CRC doesn't match, the screen flashes magenta and the databurst is requested again from the backup. If this also fails, the screen goes grey indicating that a bootcode file should be downloaded via the serial link at 115KBPS. This grey screen condition can also be forced by holding up, right and fire on a joystick in Port 1 at power up. If at any point the screen flashes yellow, there was a time-out during the EEPROM databurst.)

When the bootcode starts, the keyboard is reset, a welcome message appears (black and white text) and the system looks for an operating system.

The operating system is taken to be the first .OSF file in the root directory of the SD card. If no .OSF file is found, the bootcode looks at EEPROM address

Block 0: $0800

An operating system file is identified from its header which contains the following data:

$00 - $07 : ASCII Characters: Z80P*OS*
$08 - $0B : Length of file (excluding header)
$0C - $0D : CRC checksum of file
$0E - $0F : Not currently used (set to $0000)

Whenever an OS file is found, it is loaded to $1000, the checksum is tested and if OK, executes from $1010 (IE: a jump past the header data).

On the bootcode screen:

• ESC key: Normal OS load is aborted and a prompt for serial download of the OS code is displayed. (Left CTRL will reset the system at this point.)
• F1-F7: The FPGA will reconfigure from slot 1-7.
• F11: Set BAUD rate to 57600
• F12: Set BAUD rate to 115200